The invention relates to a semiconductor device comprising a semiconductor body with a programmable memory cell which comprises a bipolar transistor with an emitter region and a collector region of a first conductivity type mutually separated by a base region of a second, opposite conductivity type, the emitter region being coupled to a first supply line and the collector region to a second supply line: while the base region is connected through a control transistor in order to provide the bipolar transistor with a controllable base current at least temporarily during operation.
Such a device is known from the Technical Digest of the International Devices Meeting 1988, pp. 44-47. The known memory cell comprises a vertical bipolar transistor with an n-type emitter and collector region and a p-type base region, the base region being supplied through a PMOS transistor. In the known device, both the emitter region and the collector region is shared with other memory cells, and the cells are operated at a constant potential difference of approximately 6 V between the emitter and the collector regions. The PMOS transistor is connected to a combined write/read line from which a base current can be supplied to the bipolar transistor.
The known memory cell is based on the principle that electrons injected into the base region are capable of detaching electrons in the depletion zone around the base-collector junction, thus creating new free charge carriers. The charge carriers thus generated are subsequently pulled away to both sides of the depletion zone under the influence of the prevailing electric field and thereby provide an additional base current opposite to the base current supplied externally through the PMOS transistor.
If the base-emitter voltage (V.sub.BE) is sufficiently high, the additional base current gets the upper hand and the bipolar transistor continues to pass current, even if the external base current should disappear. The base-emitter voltage then remains approximately 1 V. If on the other hand only a comparatively low emitter-base voltage is applied, the externally supplied base current remains the greater and the bipolar transistor will be switched off the moment the connection with the base region is broken. The base-emitter voltage in that case is approximately 0 V. By applying a suitable potential to the base region through the PMOS transistor, it is possible to program the known cell in either of two states, corresponding to a logic "1" or "0".
The known device has the disadvantage that the memory cell consumes a comparatively high power during operation. Programmed for a logic "1", the bipolar transistor of the known memory cell carries a current of approximately 0.1 mA, which implies a power consumption of 0.6 mW per memory cell at an emitter-collector voltage of 6 V. As a result, the known device cannot be used in larger memories with, for example, one million memory cells which would require a total power of approximately 600 W on the basis of the known cell.